Power semiconductor device and the preparation method

ABSTRACT

An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

FIELD OF PRESENT INVENTION

The present invention relates to a power semiconductor package, more specifically, an ultra thin semiconductor package with high thermal dissipation performance, and the method of preparation.

BACKGROUND OF RELATED ART

In the application of power transistor, the overall size and thermal dissipation of the final semiconductor device are two important parameters. The thermal performance of the device is improved by exposing part of the electrode of the transistor, but such process is often difficult to control, and the heat dissipation is still poor. FIG. 1A is a conventional DirectFET package, which is disclosed in “DirectFET Technology—Board Mounting Application Note” January 2002—International Rectifier. Such packages are suitable for industrial applications that require extremely low conduction resistance RDSon, such as high-power DC motors, DC/AC inverter, as well as dynamic ORing hot-swap, electrical fuses and other high current switching applications. As shown in FIGS. 1A-1B, the DirectFET package includes a metal can 10 with the leads 10 a and 10 b extended horizontally at two opposite edges. A MOSFET 11 is mounted in the metal can 10, where a drain electrode at the back of the MOSFET 11 is directly attached to the metal can 10, while the top surfaces of the source electrode 11 a and the gate electrode 11 b on the front of the MOSFET 11 are coplanar with the top surfaces of the leads 10 a, 10 b of the metal can 10. Thus the source electrode 11 a, gate electrode 11 b, and two leads 10 a and 10 b can all be mounted simultaneously on the contact pads on the PCB. The DirectFET package generally has a thickness of less than 0.7 mm, thus provide an ideal solution for the compact-size power supply design in high-power industries.

FIGS. 2A-2B illustrate a conventional X-FET semiconductor package. FIG. 2A is a schematic of the lead frame 20 having a die pad 20 b with two leads 20 a extended horizontally at two opposite edges of the die pad 20 b, where the plane of the leads 20 a is higher than the plane of the die pad 20 b. As shown in FIG. 2B, the bottom electrode of a MOSFET is attached on the die pad 20 b, while the top surface of the source electrode 21 a and the gate electrode 21 b on top of the MOSFET are coplanar with the upper surface of the leads 20 a. In FIG. 2B, after the molding is completed, the MOSFET is completely covered by molding layer 25 while the source electrode 21 a, the gate electrode 21 b and the top surface of the leads 20 a are exposed from the molding layer 25 as the electrode terminals.

As shown in FIGS. 1A-1B and 2A-2B, leads 10 a, 10 b and 20 a are on opposite sides of the chip, which results in a larger package size. Furthermore, to satisfy the coplanar condition of the source and gate electrodes at the front of the chip and the top surface of the leads, the thickness of the MOSFET needs to be precisely controlled within a very narrow range, which is a great challenge to the equipment accuracy as well as cost control. In addition, in the package of FIG. 2B, the top surface of the lead 20 a is plated with a metallic layer while the gate electrode 21 b and the source electrode 21 a is protected by a tape that can be peeled after plating is done, as such the manufacturing process is more complicated.

It is within this context that embodiments of the present invention arise.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of this invention are described in more detail with reference to the accompanying drawings. However, the accompanying drawings are for the purpose of descriptions and illustrations only and do not impose limitation to the scope of the present invention.

FIGS. 1A-1B are perspective view and cross-sectional view of a conventional DirectFET.

FIGS. 2A-2B are schematic diagrams illustrating a lead frame and a complete package of a conventional X-FET package.

FIG. 3 is aerial perspective view of a lead frame of the present invention.

FIGS. 4A-4C show the process of manufacturing a lead frame of FIG. 3 with a thin film layer attached on top.

FIGS. 5A-5H show a process for preparing the power semiconductor device of the present invention.

FIGS. 6A-6D show alternative power semiconductor devices of the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

FIG. 3 shows a lead frame unit 101, which can be made of copper, with its upper surface covered with a thin layer 102. The lead frame unit 101 has a staggered structure including an upper metal section 101 b and a lower metal section 101 a with their top surfaces being parallel to each other. A plurality of contact holes 103 a are formed atop the upper section 101 b by etching through the thin layer 102, exposing the metal section 101 b. These contacts holes are preferred to be in a straight row. Similarly, an opening 103 b is also formed by etching through the thin layer 102 atop the lower metal section 101 a exposing the lead frame. Optionally, the opening 103 b can be a square shape to accommodate a square chip and the contact holes 103 a are circular to accommodate solder balls.

FIGS. 4A-4C show the preparation steps of the lead frame unit 101 of FIG. 3. As shown in FIG. 4A, a flat metal layer 1010 with a thin layer 102 formed on top is provided. The thin layer, which is preferably aluminum, can be formed by plating, sputtering or lamination atop the metal layer 1010. Then a photoresist layer is applied on thin layer 102 (not shown) followed by the etching of the thin layer 102 to form the contact holes 103 a in the area 102-1 and the opening 103 b in the area 102-2, and then the photoresist layer is removed as shown in FIG. 4B. As shown in FIG. 4C, the metal layer 1010 with the etched layer 102 formed thereon is bent, through punching or stamping, forming an upper section 101 b and a lower-set section 101 a. With reference to FIGS. 4B-4C, the portion 1010-1 of the metal layer 1010 with the contact holes 103 a in the area 102-1 is punched to form the upper section 101 b, while the portion 1010-2 of the metal layer 1010 with the opening 103 b in the area 102-2 becomes the lower section 101 a. The inclined section between the upper section 101 b and the lower section 101 a is completely covered by thin layer 102. The material used for thin layer 102 needs to be ductile; otherwise crack may result during punching process or at the bend. This will be described in detail later.

FIG. 5A shows a portion of a lead frame strip 200 comprising a plurality of lead frame units 101 of FIG. 3 connected together. The layout of the lead frame unit 101 on the lead frame strip 200 can be varied, for example the lead frame includes all the lead frame units in the strip oriented in the same way or the lead frame strip includes a plurality of pairs of two adjacent lead frame units arranged as a mirror image of each other. In FIG. 5B, a conductive adhesive material, such as solder paste or silver paste, is applied to the surface of the opening 103 b in the lower section 101 a (not shown), then a vertical type power MOSFET chip 104 is attached on the opening 103 b via the conductive adhesive material, such that the electrode at the bottom of the chip 104, for example drain electrode, is electrically connected to the lead frame unit 101. This step can also be achieved by using an Eutectic soldering. In FIG. 5C, a metal bump 105 a are deposited into each of the contact holes 103 a on the upper section 101 b, a metal bump 105 c is deposited on the gate electrode 104 a of the MOSFET chip 104 while a plurality of metal bumps 105 b are deposited on the source electrode 104 b of the same chip. These metal bumps can be made by solder ball drop, solder print or solder dispensed. When solder balls are used, reflow soldering is used for the attachment.

The thin film layer 102 is preferably made of aluminum since solder bumps 105 a and 105 b generally have better wettability by copper than by aluminum. Hence the metal bumps 105 a are formed on the copper surface in the contact holes 103 a at the top surface of upper section 101 b without wetting and overflowing on the top surface of the aluminum layer 102 surrounding the contact holes 103. Further, the oxidation of the aluminum layer 102 forms a passivation layer that further help preserve the shape of the solder bumps since the solder does not have a good wettability by aluminum oxide. The oxidation occurs at an exposed top surface of the aluminum layer 102. An optional aluminum oxide layer 192 is shown in dashed lines in FIG. 5D. Aluminum is an example of the material used as the thin layer 102; however any metal to which the solder does not have a better wettability than the material of the lead frame can be used for the thin layer.

In FIG. 5E, plastic material, such as epoxy resin, is deposited to form a molding layer 106 covering the thin layer 102, the lead frame strip 200 comprising a plurality of lead frame units 101, chips 104, and all the metal bumps 105 a, 105 b and 105 c, while the bottom surface of the lower section 101 a is exposed. Material for the thin layer 102 is selected so that its binding strength to the molding layer is stronger than that between the molding layer and the lead frame. Thus when oxidation occurs on the surface of layer 102, its surface is rougher and the bonding strength between the thin layer 102 and the molding layer 106 is even better.

In FIG. 5F, after the molding process, a metal layer 107 is optionally plated on the exposed bottom surface of lower section 101 a of every lead frame unit. An example of this step is electroplating of a tin layer. Then, as shown in FIG. 5G, the molding layer and the metal bumps 105 a, 105 b and 105 c are ground from the top until the metal bumps 105 a, 105 b and 105 c are exposed and flushed with the molding layer 106. In FIG. 5H, individual packages 1060 are formed by separating the lead frame units 101 from each other and from the lead frame strip 200. Each package 1060 consists of a lead frame unit 101 with a thin layer 102 formed thereon, a chip 104 attached to the lead frame unit 101, metal bumps 105 a, 105 b and 105 c attached on the chip 104 and the upper section 101 b of the lead frame unit and exposed from the molding layer, and the bottom surface of the lower section of the lead frame unit exposed from the molding layer. As mentioned above, the exposed bottom surface is optionally plated with a metal layer 107.

FIG. 6A shows the top view of the semiconductor package according to an embodiment of the present invention, which includes the metal bumps 105 a, 105 b, 105 c with the flat surfaces exposed from the molding layer and FIG. 6B shows the bottom view of the same semiconductor package with the bottom surface of the lower section of the lead frame unit exposed from the molding layer, which may be plated with a metal layer.

FIG. 6C shows a top view of a semiconductor package according to an alternative embodiment. For a semiconductor device with a large current flowing through the source electrode, more metal bumps 105 b may be placed on the source electrode 104 b, which will increase the current flow and reduce the on-resistance. FIG. 6D shows another alternative semiconductor package, where a large metal bump 105 b′ is formed on source electrode 104 b, resulting in a larger exposed area, enabling it to carry larger currents and reduce the on-resistance. The semiconductor device shown in FIG. 6D can be formed with a similar method shown in FIGS. 5A-5H, excepting that the density of the metal bumps 105 b is increased, such that adjacent metal bumps are placed closer to each other, and in the reflow step, the metal bumps 105 b are melted and are merged together forming the metal bump 105 b′. In this embodiment, metal bumps 105 a on the contact holes 103 a also begin to melt but the thin layer 102 prevents them from merging with each other.

In a preferred embodiment as shown in FIG. 5D, the top surface of the upper section 101 b of the lead frame unit is coplanar with the top surface of the chip 104, thus the areas of the exposed flat surfaces of the metal bumps 105 b and 105 a in FIG. 5G are substantially equal, which is easy for butt welding on the standard size pads on the PCB. However, this embodiment does not limit the scope of the present invention. In the present invention, the top surface of the upper section 101 b can be slightly higher or lower than the top surface of the chip 104, after the molding step, the top surface of metal bumps 105 a, 105 b, 105 c are ground, as shown in FIG. 5G, and they are coplanar with each other and also with the top surface of the molding layer. In this case, the exposed areas of the metal bumps 105 a, 105 b, 105 c are different, thus the areas of the corresponding contact on the PCB need to be adjusted. Therefore there is a big range for the thickness of the chip 104 or the difference in height between the lower and the upper sections, which cannot be achieved in the prior art manufacturing process.

Comparing with the can structures of the conventional lead frames in FIG. 1A and FIG. 2A, the lead frame unit 101 only includes one extended edge, as such the overall size of the lead frame is reduced for the same size chip. With the manufacturing process of the present invention, the overall thickness of the semiconductor device 1060 is about 0.25 mm to 0.35 mm, thus the semiconductor device is ultra thin and lightweight.

While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.” 

The invention claimed is:
 1. A preparation method of a power semiconductor device, the method comprising the steps of: providing a lead frame strip comprising a plurality of lead frame units each having a respective staggered structure with a respective upper section and a respective lower section, wherein a respective thin layer is laminated atop a top surface of said each lead frame unit, and wherein the respective thin layer comprises a plurality of contact holes located on the respective upper section and at least one opening located on the respective lower section of said each lead frame unit; attaching a respective semiconductor chip inside the at least one opening on the respective lower section of said each lead frame unit; depositing a plurality of metal bumps onto the plurality of contact holes in the respective upper section of said each lead frame unit and onto electrodes on a top surface of the respective semiconductor chip; and cutting the lead frame strip to separate individual lead frame units; wherein the step of providing the lead frame strip comprising the plurality of lead frame units comprises the sub-steps of: providing a flat lead frame strip having a flat thin layer laminated on a top surface of the flat lead frame strip, the flat lead frame strip further having a plurality of flat lead frame units, the flat thin layer having a plurality of flat thin layer sections, a respective flat thin layer section of the plurality of flat thin layer sections being on top of each of the flat lead frame units; selectively etching through the flat thin layer so as to form a plurality of contact holes and at least one opening on the respective flat thin layer section; and punching said each of the flat lead frame units to form a respective staggered structure, wherein a first respective portion with the plurality of contact holes becomes the respective upper section and a second respective portion with the at least one opening becomes the respective lower section.
 2. The method of claim 1, wherein the flat thin layer is formed by laminating an aluminum layer on the top surface of the flat lead frame strip.
 3. The method of claim 1 further comprising: forming a molding layer covering the lead frame strip laminated with the flat thin layer, the semiconductor chips, and the plurality of metal bumps after the step of depositing the plurality of metal bumps, wherein a bottom surface of the lower section of said each lead frame unit is exposed from the molding layer; grinding the molding layer and the plurality of metal bumps so that flat top surfaces of the metal bumps are exposed from a top surface of the ground molding layer; and cutting the lead frame strip and molding layer to separate individual power semiconductor devices.
 4. The method of claim 3 further comprising plating a metal layer on the exposed bottom surface of the lower section of said each lead frame unit before the step of grinding the molding layer.
 5. The method of claim 3, wherein the flat thin layer is an aluminum film with a layer of aluminum oxide as a passivation layer on a top surface of the aluminum film, and wherein the passivation layer establishes a strong bonding with the molding layer.
 6. The method of claim 1, wherein a top surface of the respective upper section of said each lead frame unit is coplanar with the top surface of the respective semiconductor chip. 